As semiconductor devices shrink to 0.18 μm, 0.15 μm and 0.13 μm design rules and beyond, the side wall spacer width performance is sensitive to electric test parameters such as Isat N(P), Rser (N)P and RS N+P+. This will also affect the wafer acceptance test (WAT) parameters and subsequent silicide formation.
Composite side wall spacer formation is more complex in the etching module and the spacer width is difficult to control with different pattern densities. This results in unstable Isat and/or silicide bridging issues.
U.S. Pat. No. 6,268,253 B1 to Yu describes a removable spacer process.
U.S. Pat. No. 5,899,722 to Huang describes a double spacer process.
U.S. Pat. No. 5,879,998 to Krivokapic describes a short channel device with double spacers.